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| confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 1 map7 102 C dual output lcd bias ic ordering information part number top marking junction temperature range package rohs status map 7102 wcrh 7102 lll ywn mm - 40 to + 8 5 15 bump 0.4mm pitch csp halogen free m ap7 102 dual output lcd bias ic general description the map7102 is designed to support positive / negative driven tft - lcd panels . the two output rails are usually connected to the source driver ic. the device uses a single inductor scheme in order to provide the user the smallest solution size possible as well as high efficiency. with its input voltage range of 2. 8 v to 5.5v, it is optimized for products powered by single - cell batteries and output current s up to 5 0ma. the device is delivered in a w l csp package of 15 balls. features ? simo(single - inductor multiple output) regulator technology ? 86 % efficiency for 20 ma load current between +5 .0 v and - 5 .0 v. ? 2. 8 v to 5.5v input voltage range ? under - v ol tage lockout rising/falling ? programmable output voltages ? positive output voltage range : 4.0v to 5.7 v ( 0.1v step ) ? negative output voltage range : - 4.0v to - 5.7 v ( 0.1v step ) ? 1 % (typ.) output voltage accuracy ? maximum output current : 5 0ma ? programmable active discharge ? excellent line regulation ? advanced power - save mode for light - load efficient ? integrated compensation and feedback circuits ? fully integrated fets for synchronous rectification ? short circuit protection ? thermal shutdo wn protection ? 15 - ball wl csp package application : ? tft lcd smartphones ? tft lcd tablets ? general dual power supply applications
confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 2 map7 102 C dual output lcd bias ic block diagram application circuit r e g v p o s o u t p o u t n a g n d c f l y 1 c f l y 2 p g n d s d a s c l e n p e n n v i n v i n v n e g 5 . 0 v / 4 0 m a - 5 . 0 v / 4 0 m a l d o c p n s y n c b o o s t s w v i n e n p e n n s c l s d a p g n d a g n d s w o u t p r e g o u t n c f l y 1 c f l y 2 v p o s 5 . 0 v / 4 0 m a - 5 . 0 v / 4 0 m a v n g e l 4 . 7 u h c 1 4 . 7 u f v i n 2 . 8 v t o 5 . 5 v c 3 4 . 7 u f c 2 4 . 7 u f c 5 4 . 7 u f c 4 2 . 2 u f e n p e n n s c l s d a confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 3 map7 102 C dual output lcd bias ic bill of materials : item part number manufacturer description qty. pmic map 7 102 magnachip dual output dc - dc 1 lx dfe25201 2 c toko 4 . 7 uh , 1 . 6 a, 250 mohm, 1 c 4 grm188 r61c225kaad murata 2 . 2 f, 16 v, 0603, x5r, ceramic 1 c1/ c2/ c 3 / c 5 grm188r61 c475kaaj murata 4.7 f, 16 v, 0603, x5r, ceramic 4 pin configuration pin description pin na me pin number description enn a1 enable pin for v neg rail outn a2 output pin of the negative charge pump (v neg ) cfly2 a3 negative charge pump flying capacitor pin enp b1 enable pin for v pos rail scl b2 i2c interface clock signal pin pgnd b3, e1 power ground vin c1 input voltage supply pin sda c2 i2c interface data signal pin cfly1 c3 negative charge pump flying capacitor pin sw d1 switch pin of the boost converter top view bottom view b a l l a 1 p g n d r e g o u t p s w a g n d r e g v i n s d a c f l y 1 e n p s c l p g n d e n n o u t n c f l y 2 e 1 e 2 e 3 d 1 d 2 d 3 c 1 c 2 c 3 b 1 b 2 b 3 a 1 a 2 a 3 confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 4 map7 102 C dual output lcd bias ic agnd d2 analog ground reg d3, e2 boost converter output pin outp e3 output pin of the ldo (v pos ) absolute maximum ratings absolute maximum ratings (note ) parameter value unit cfly1,outp, reg, scl, sda, vin - 0.3 to 6 . 0 v enp, enn - 0.3 to v in + 0.3v v sw - 0.3v to voutp+0.3 v cfly2, outn - 6 . 0 to 0.3 v operating ambient tempera ture range, t a - 40 to +85 ambient storage temperature (ts) - 65 to +150 junction thermal resis tance ( ja ) (note) 76.5 /w esd hbm rating 2 kv esd mm rating 200 v note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. recommended operating conditions parameter value unit input voltage range 2 . 8 to 5.5 v inductor 2.2 to 4.7 uh input capacitor 4.7 to 10 uf flying capacitor 2.2 to 4.7 uf output capacitor 4.7 to 10 uf oper ating ambient temperature - 40 to +85 operating junction temperature - 40 to +125 confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 5 map7 102 C dual output lcd bias ic electrical characteristics v in = 3. 8 v, enn = enp = v in , v pos = 5. 0 v, v neg = C 5. 0 v, t a = C 40c to 85c; typical values are at t a = 25c (unless otherwise noted). symbol paramete r test conditions min. typ. max. unit g eneral section v in input voltage range 2. 8 5. 5 v v uvlo under voltage lock out rising threshold voltage 2. 6 2. 8 v falling threshold voltage 2. 1 2. 3 v iq(on) quiescent current enable=high, switching mode 1.3 m a iq(off) shutdown current enable=low 1 3 ua v ih enable high threshold 1. 2 v v il enable low threshold 0.4 v r en enable pull down resistance en_p/n (note1) 2 00 k ? t sd thermal shutdown temperature (note1) 1 4 0 t sd_hys thermal shutdown hysteresis (note1) 10 boost converter _ v reg i lim vreg v reg current limit (note1) 0.9 1. 2 1. 5 a f sw boost switching fre q u e n cy 1.44 1.8 2.25 mhz r onlxpg internal mosfet swi tch on - resistance from lxp to gnd iout= 10 0ma (note1) 175 m? r onlxpo internal mosfet switch on - resistance from lxp to vbst iout= 10 0ma (note1) 240 m? i lxplx lx leakage current vlxp=5.0v, en=0v 10 ua tss soft start time (note1) 0.7 2 ms negativ e charge pump output _ vneg v neg negative output voltage range - 4.0 - 5.7 v vneg output voltage accuracy 2.8 v confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 7 map7 102 C dual output lcd bias ic typical characteristics v in = 3. 8 v, v pos = 5. 0 v, v neg = C 5. 0 v, unless otherwise noted table of graphs efficiency [vpos=5.0v,vneg= - 5.0v] figure 1. efficiency C inductor [4.7uh] power on sequence figure 3. power on sequence vpos ripple figure 5. power up/down with fast discharging quiescent current vs. input voltage figure 2. quiescent current power off sequence figure 4. power off sequence vneg ripple figure 6 . v neg ripple confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 8 map7 102 C dual output lcd bias ic vpos output light load figure 7 . vpos output voltage C light load(10ma) vneg output light load figure 9 . vneg output voltage C light load(10ma) vpos output voltage vs. input voltage figure 1 1 . line regulation C vpos=5.0v vpos output heavy load figure 8 . vpos output voltage C heavy load(40ma) vneg output heavy load figure 1 0 . vneg output voltage C heavy load(40ma) vneg output voltage vs. input voltage figure 1 2 . line regulation C vneg= - 5.0v confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 9 map7 102 C dual output lcd bias ic vpos output voltage vs. load current figure 1 3 . load regulation C vpos=5.0v load transient figure 1 5 . load regulation [ vin=2.9v, iout=45ma ] power up/down with fast discharging figure 17. power up/down with fast discharging vneg output voltage vs. load current figure 1 4 . load regulation C vneg= - 5.0v load transient figure 1 6 . load regulation [ vin=3.8v, iout=45ma ] confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 10 map7 102 C dual output lcd bias ic applications under - voltage lockout if the input voltage falls below the v uvlo level of 2.1v, all the dc/dc regulators of map7102 are disabled, and all the r ails will restart with soft - start when input voltage is applied again enp/enn the enp pin c ontrols the output of vpos and the enn pin controls the output of vneg. a high on either enp or enn will enable the boost converter vreg. vpos, vneg and vreg re quire both their respective en pin high for each to be enabled power on / off sequence the vreg boost regulator is activated when the input voltage is higher than the uvlo threshold, and ei ther enp or enn are high. the vpos output is activated if enp i s high and vreg has completed its soft - start. the vneg output is activated if enn is high and vreg has completed its soft - start. enp or enn being pulled low shuts down vpos or vneg, respectively. i f both enp and enn are pulled low, vpos, vneg and vreg are all turned off the discharge resistors of the vpos and vneg output are 70 ? and 20? resp ectively. figure 18 : example of power on sequence when enn figure 19 : example of power on sequence when both enp r ising after vp os soft - start finished and enn rising before v reg soft - start finished v i n e n p e n n v r e g v r e g p o w e r g o o d v p o s v n e g u v l o 0 . 7 m s 0 . 7 m s 0 . 7 m s v i n e n p e n n v r e g v r e g p o w e r g o o d v p o s v n e g u v l o 0 . 7 m s 0 . 7 m s 0 . 7 m s confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 11 map7 102 C dual output lcd bias ic figure 20 : example of power off sequence activated figure 21 : example of power off sequence activated by enp and en n when vin is above uvlo by vin falling below uvlo register map slave address : 3eh [ bit : 0 111110x ] table 1 . i2c registers register r/w function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h r/w vpos not used vpos[4] vpos[3] vpos[2] vpos[1 ] vpos[0] 01h r/w vneg not used vneg[4] vneg[3] vneg[2] vneg[1] vneg[0] 03h r/w dis not used disp disn table 2. vpos/vneg voltage setting no. code hex vpos vneg bit4 bit3 bit2 bit1 bit0 1 0 0 0 0 0 00h 4.0v - 4.0v 2 0 0 0 0 1 01h 4.1v - 4.1v 3 0 0 0 1 0 02h 4.2v - 4.2v 4 0 0 0 1 1 03h 4.3v - 4.3v 5 0 0 1 0 0 04h 4.4v - 4.4v 6 0 0 1 0 1 05h 4.5v - 4.5v 7 0 0 1 1 0 06h 4.6v - 4.6v 8 0 0 1 1 1 07h 4.7v - 4.7v 9 0 1 0 0 0 08h 4.8v - 4.8v 10 0 1 0 0 1 09h 4.9v - 4.9v 11 0 1 0 1 0 0ah 5.0v - 5.0v v i n e n p e n n u v l o v r e g v r e g p o w e r g o o d v p o s v n e g p u l l t o g n d ( 2 0 o h m t y p ) p u l l t o g n d ( 7 0 o h m t y p ) v i n e n p e n n u v l o v r e g v r e g p o w e r g o o d v p o s v n e g p u l l t o g n d ( 2 0 o h m t y p ) p u l l t o g n d ( 7 0 o h m t y p ) confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 12 map7 102 C dual output lcd bias ic n o. code hex vpos vneg bit4 bit3 bit2 bit1 bit0 12 0 1 0 1 1 0bh 5.1v - 5.1v 13 0 1 1 0 0 0ch 5.2v - 5.2v 14 0 1 1 0 1 0dh 5.3v - 5.3v 15 0 1 1 1 0 0eh 5.4v - 5.4v 16 0 1 1 1 1 0fh 5.5v - 5.5v 17 1 0 0 0 0 10h 5.6v - 5.6v 18 1 0 0 0 1 11h 5.7v - 5.7v i 2 c bus control i 2 c interface data transmission from the main u p to map7102 and vice versa takes place through the i 2 c bus interface, consisting of the two lines sda and scl (pull - up resistors to a positive supply voltage must be externally connected) interface protocol the interface protocol is composed of five commands below table. table 3 . i 2 c protocol commands command type description state start condition a start condition scl=1, sda 1 to 0 stop c ondition a stop condition scl=1, sda 0 to 1 device addr + w/r byte a device address and w/r write=0 / read=1 addr byte a register address byte - data byte a data byte - the register address byte determines the first register in which the read or write operation takes places. when the read or wri te operation is finished, the register address is automatically incremented. table 4 . i2c packet format start 7 6 5 4 3 2 1 0 ack 7 6 5 4 3 2 1 0 ack 7 6 5 4 3 2 1 0 ack stop device address (7bit) r/w register address (8bit) data (bit) start and stop conditions both data and clock lines remain high when the bus is not busy. as shown in below figure, a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. a stop condition must be sent before each start condition. confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 13 map7 102 C dual output lcd bias ic fig ure 22 timing diagram on i 2 c bus data validity the data on the sda line must be stable during the high period of the clock. the high and l ow state of the data line can only change when the clock signal on the scl line is low. fig ure 23 data validity on i 2 c bus data acknowlege the master ( u p) puts a resistive high level on the sda line during the acknowle dge bit. the msb is transferred first. one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse. any change in the sda line at this time will be interpreted as a control sign al. fig ure 24 data acknowledge on i 2 c bus writing to a single register writing to a single register starts with a start bit followed by the 7 bit device address of map7102 . the 8th bit is the w/r bit, which is 0 in this case. w/r=1 means a reading operation. then the master waits for an acknowledge from map 7102 . then the 8 bit address of register is sent to map 7102 . it is also followed by an acknowledge pulse. the last transmitted byte is the data that is going to be wr itten to the register. it is again followed by an acknowledge pulse from map 7102 . the master then generates a stop bit and the communication is over. s c l s d a s t a r t s t o p s c l s d a d a t a l i n e s t a b l e d a t a v a l i d d a t a c h a n g e a l l o w e d 1 2 3 4 5 6 7 8 9 m s b l s b s t a r t a c k n o w l e d g e m e n t f r o m s l a v e s c l s d a confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 14 map7 102 C dual output lcd bias ic fig ure 25 writing to a single register writing to multiple registers w ith incremental addressing it would be unpractical to send several times the device address and the address of the register when writing to multiple registers. map 7102 supports writing to multiple registers with incremental addressing. when data is writte n to a register, the address register is automatically incremented. s o the next data can be sent without sending the device address and the register address again. figure 26 writing to multiple registers reading from a sin gle register the reading operation starts with a start bit followed by the 7bit device address of map 7102 . the 8 - th bit is the w/r bit, which is 0 in this case. map 7102 confirms the receiving of th e address + w/r bit by an acknowledge pulse. the address o f the register which should be read is sent afterwards and confirmed again by an acknowledge pulse of map 7102 again. then the master generates a start bit again and sends the device address followed by the w/r bit, which is 1 now. map 7102 confirms the rece iving of the address+ w/r bit by an acknowledge pulse and starts to send the data to the master. no acknowledge pulse from the master is required after receiving the data. then the master generates a stop bit to terminate the communication. figure 27 reading from a single register s t r t s t o p m s b l s b l s b m s b m s b l s b 7 b i t d e v i c e a d d r e s s w / r a c k a c k a c k 8 b i t a d d r e s s o f r e g i s t e r d a t a w r t s c l s d a 7 b i t d e v i c e a d d r e s s 8 b i t a d d r e s s o f r e g i s t e r i d a t a i d a t a i + 1 d a t a i + n - 1 d a t a i + n m s b l s b l s b m s b m s b l s b w / r a c k a c k a c k l s b m s b m s b l s b a c k a c k a c k w r t m s b l s b s c l s d a 7 b i t d e v i c e a d d r e s s 8 b i t a d d r e s s o f r e g i s t e r d a t a 7 b i t d e v i c e a d d r e s s s t r t m s b l s b l s b m s b m s b w / r a c k a c k l s b a c k w / r s t r t s t o p a c k w r t r e a d n o a c k m s b l s b s c l s d a confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 15 map7 102 C dual output lcd bias ic reading from multiple registers with incremental addressing reading from multiple registers starts in the same way like reading from a single register. as soon as the first register is rea d, the register address is automatically incremented. i f the master generates an acknowledge pulse after receiving the data from the first register, then reading of the next register can start immediately without sending the device address and the register address again. the last acknowledge pulse before the stop bit is not required. fig ure 28 reading from multiple registers 7 b i t d e v i c e a d d r e s s 8 b i t a d d r e s s o f r e g i s t e r d a t a i 7 b i t d e v i c e a d d r e s s s t r t m s b l s b l s b m s b m s b w / r a c k a c k l s b a c k w / r s t r t d a t a i + 1 d a t a i + n - 1 d a t a i + n a c k m s b l s b a c k m s b l s b a c k m s b l s b a c k m s b l s b s t o p r e a d w r t n o a c k s c l s d a confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 16 map7 102 C dual output lcd bias ic p ackage information e : 15 5 0 30um . d : 21 50 30um . confidential datasheet version 1 . 1 mar . 20 1 5 . revision 1 . 1 magnachip semiconductor ltd . 17 map7 102 C dual output lcd bias ic r evision histroy date version changes 2013.05.07 0.0 initial release. 2013.06.27 0.1 vpos/vneg output voltage range : 6.0v ? 5.7v, - 6.0v ? - 5.7v register map change. 2013.11.2 2 0.2 electrical characteristic spec updated - maximum current : 80ma ? 50ma - external component change - vpos/vneg line & load regulation ? test condition & spec change 2014.01.21 0.3 maximum rate spec updated - all control pin : - 0.3v to 6.6v ? - 0.3v to 6.0v - sw pin spec : - 0.3v to 6.6v ? - 0.3v to voutp +0.3v 2014.09.15 0.4 add to graph input voltage range change : min 2.5v ? min 2.8v vpos/vneg load regulation spec change : vneg : 6mv ? 0.19 %/ m a, vpos : 5mv ? 0.31 %/ m a boost current limit & rds(on) : design guaranteed 201 5 . 01 . 27 1.0 final datasheet 201 5.03.31 1.1 uvlo rising threshold voltage : 2.3v ? 2.6v |
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